1. Field of the Invention
The present invention relates, generally, to an organic memory device having a memory active region formed by an embossing structure, and more particularly, to an organic memory device in which a memory active region is formed, thereby decreasing distribution of switching time, resulting in increased reliability of the device.
2. Description of the Related Art
With the remarkable development of information and communication industries, the demand for various memory devices has drastically increased. In particular, memory devices necessary for portable terminals, smart cards, digital cameras, games, MP3 players, etc., require nonvolatile characteristics. Nonvolatile memory, such as flash memory based on a silicon material, is mainly used.
However, conventional flash memory is disadvantageous because it has a limited number of recording/erasing times and slow recording speed. Moreover, manufacturing cost for increasing the degree of integration is high, and manufacturing techniques of the chips are difficult, making them incapable of being further miniaturized. Thus, thorough attempts have been made to develop next-generation nonvolatile memory devices that realize ultrahigh speeds, high capacities, low prices and ultra-small sizes, overcoming the physical limitations of conventional silicon flash memory.
In this regard, the next-generation memory devices are classified into ferroelectric random access memory (RAM), magnetic RAM, phase-change RAM, nanotube RAM, holographic memory, organic memory, etc., depending on the type of material constituting a unit cell in a semiconductor.
Of these memory devices, organic memory achieves memory capability using bistability of resistance resulting from the application of voltage to an organic material provided between upper and lower electrodes. FIG. 1 is a schematic cross-sectional view showing an organic memory device according to a conventional technique. As shown in FIG. 1, such a conventional organic memory device is formed by including an organic memory layer 400 between a first electrode 300 and a second electrode 500 on a substrate 100.
The memory operation of the organic memory device is realized by reversible switching between at least two resistance states. FIG. 2 is a graph showing voltage relative to switching time of a conventional organic memory device. As is apparent from FIG. 2, in the case where a uniform voltage pulse is applied to the memory device for switching, an actual response of the device occurs after a predetermined time delay from the application of voltage, rather than occurring immediately upon application of the voltage. As the demand for high-speed devices has gradually increased in recent years, the switching speed of the memory device has also become faster, to 40 nanoseconds (ns) or less. However, the switching delay time is relatively slow, such as to ones of to tens of microseconds (μs), and is thus problematic.
Unlike a conventional silicon-based memory device, which is typically manufactured in a sterile environment, the organic memory device may be manufactured by a relatively inexpensive process, such as a solution process. Since the organic memory device may be manufactured in a working environment where the cleanliness cannot be expected, the organic memory device may be readily exposed to contaminants such as dust. Therefore, as sown in FIG. 1, dust or defects 50 may be generated between the substrate 100 and the first electrode 300. If so, the thickness of the organic memory layer 400 of the organic memory device may become non-uniform. The organic memory layer 400 of the organic memory device may be prepared to a thickness of 20 to 100 nanometers (nm) and fine dust of 100 nm or less may greatly negatively affect performance of the device.
Since a portion of the organic memory layer 400 thickness decreased by and that is relatively thin due to the dust or defects 50 requires the application of high current or electrical field, switching by current or electrical field may increasingly occur at the portion of the organic memory layer 400 where dust is present or defects 50 are generated. In addition, the memory device having dust or defects has a non-uniform or very wide distribution of switching delay time attributed to the irregular generation of dust or defects, undesirably increasing defect rates upon manufacturing of the memory device and causing a problem of deteriorating switching precision and accuracy of the finally manufactured memory device. If the memory device has too wide a distribution of switching delay time, the memory device may not be capable of functioning or applied as a memory device.
In the case where fine dust or defects occur during manufacturing processes of the memory device, generation frequencies of such defects are in proportion to the total area of an active region. The memory device that may be composed of hundreds of millions of cells may be targeted for decrease the total area of the cells through reduction of the size of a unit cell and additional difficulties may be incurred in terms of cost and process.